This invention relates to the field of integrated circuit development and design. More particularly, this invention relates to improved methods and apparatuses for analyzing logic circuits to reduce testing time.
Integrated circuits are tested to determine proper functionality and the existence of defects which may introduce faults in the integrated circuit during use. Current sampling and analysis techniques are limited by currently available hardware and software. For example, integrated logic analyzers have been used with integrated circuits to monitor and trace signals during circuit analysis. However, such analyzers are typically limited to trace speeds of about one hundred and fifty-five megahertz and up to about 256 signals. As the speed of the integrated circuits and memory devices increases, sampling speeds higher than about one hundred and fifty-five megahertz are desirable so that there is a more complete capture of the traces for analysis of the circuit. More accurately capturing high speed signals would enable a reduced debug time, thereby saving production costs for the integrated circuits.
Another disadvantage of current analysis techniques for integrated circuits is that the simulation and analysis of the circuits is often limited by the speed at which the analytical tools can process the scan information input to the circuits. Conventional analysis tools run simulation generated vectors for fault coverage and functional analysis of the integrated circuit by use of input output pins in the circuit. However, internal nodes and high speed circuits may or may not be adequately tested. Failure analysis of the circuit is difficult to perform without considerable time and effort. Furthermore, fault coverage improvement is limited by the tool capabilities. Once the fault coverage report is generated, fault coverage improvement is often added manually. Hence, there exists a need to provide analysis tools and methods which reduce testing time and provide more automated analysis of circuits to improve fault coverage for higher yield of useable parts.
The above and other needs are met by an apparatus and method for using the apparatus to reduce analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing an integrated circuit having a predetermined functionality. Means are provided for accelerating circuit analysis, the means being selected from the group consisting of a high speed sampling circuit coupled to the integrated logic analyzer and an on-board circuit testing and analysis apparatus including the integrated logic analyzer.
In another aspect the invention provides a method for high speed sampling of digital signals running above about one hundred and fifty-five megahertz. The method includes the steps of providing a high speed sampling circuit coupled to an integrated logic analyzer including sampling circuit registers running at about one gigahertz or more, capturing signals in about one half of the sampling circuit registers, the signals having a value different from a previous value in the registers, and storing the captured signals and a real time clock value corresponding to the captured signals in one-half of the sampling circuit registers.
In yet another aspect, the invention provides a method for integrated circuit analysis. The method includes the steps of providing an on board circuit testing and analysis circuit including a test bench simulation circuit for simulated signal feed and simulated signal capture of selected internal points, the test bench simulation circuit including an integrated circuit analysis device, and programming the integrated logic analyzer to reduce integrated circuit analysis time.